Type of Document	Dissertation
Author	Murali, Raghunath
URN	etd-02132004-173432
Title	Scaling Opportunities for Bulk Accumulation and Inversion MOSFETs for Gigascale Integration
Degree	Doctor of Philosophy
Department	Electrical and Computer Engineering
Advisory Committee	Advisor Name Title Meindl, James Committee Chair Allen, Phillip Committee Member Cressler, John Committee Member Davis, Jeffrey Committee Member Hess, Dennis Committee Member
Keywords	MOSFET buried channel inversion accumulation threshold voltage short channel effect
Date of Defense	2004-02-06
Availability	unrestricted
Abstract The objective of this research is to comprehensively compare bulk accumulation and inversion MOSFETs, and find application areas where each is superior.Short channel effect (SCE) models for accumulation and inversion MOSFETs are derived that accurately predict threshold voltage, subthreshold swing, and subthreshold current. A source/drain junction depth dependent characteristic length is derived that can be used to rapidly assess the impact of junction depth scaling on minimum channel length. A fast circuit simulation methodology is developed that uses physically based I-V models to simulate inversion and accumulation MOSFET inverter chains, and is found to be accurate over a wide range of supply voltages. The simulation methodology can be used for rapid technology optimization, and performance prediction. Design guidelines are proposed for accumulation MOSFET design; the guidelines result in a low process sensitivity, low SCE, and a subthreshold current less than the allowable limit. The relative performance advantage of accumulation/inversion MOSFETs is gate-technology dependent. In critical comparisons, on-current is evaluated by means of a full band Monte Carlo device simulation. Gate-leakage, and band-to-band tunneling leakage at the drain-substrate region are included in the performance analysis. For mid-bandgap metal gate, accumulation MOSFETs perform better than inversion MOSFETs for hi-performance (HiP) and low-operating power (LOP) applications. For tunable metal gate technology, inversion MOSFETs always perform better than accumulation MOSFETs. For dual poly technology, accumulation MOSFETs perform better than inversion MOSFETs for low standby power (LSTP) applications. A comprehensive scaling analysis has been performed on accumulation and inversion MOSFETs using both SCE models and 2-D simulations. Results show that accumulation MOSFETs can scale better than inversion MOSFETs for mid-bandgap metal gate HiP, and LOP applications; and poly gate LSTP applications.
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