Type of Document	Dissertation
Author	Tan, Yudong
Author's Email Address	yudong.tan@gmail.com
URN	etd-04132005-212947
Title	CACHE DESIGN AND TIMING ANALYSIS FOR PREEMPTIVE MULTI-TASKING REAL-TIME UNIPROCESSOR SYSTEMS
Degree	Doctor of Philosophy
Department	Electrical and Computer Engineering
Advisory Committee	Advisor Name Title Mooney, Vincent Committee Chair Meliopoulos, A. P. Sakis Committee Member Prvulovic, Milos Committee Member Schimmel, David Committee Member Yalamanchili, Sudhakar Committee Member
Keywords	Real-time system Multi-tasking Cache Timing Analysis
Date of Defense	2005-04-05
Availability	unrestricted
Abstract In this thesis, we propose an approach to estimate the Worst Case Response Time (WCRT) of each task in a preemptive multi-tasking single-processor real-time system utilizing an L1 cache. The approach combines inter-task cache eviction analysis and intra-task cache access analysis to estimate the Cache Related Preemption Delay (CRPD). CRPD caused by preempting task(s) is then incorporated into WCRT analysis. We also propose a prioritized cache to reduce CRPD by exploiting cache partitioning technique. Our WCRT analysis approach is then applied to analyze the behavior of a prioritized cache. Four sets of applications with up to six concurrent tasks running are used to test our WCRT analysis approach and the prioritized cache. The experimental results show that our WCRT analysis approach can tighten the WCRT estimate by up to 32% (1.4X) over prior state-of-the-art. By using a prioritized cache, we can reduce the WCRT estimate of tasks by up to 26%, as compared to a conventional set associative cache.
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